The present invention relates generally to semiconductor processing, and in particular to a system for monitoring critical dimensions in a latent image and controlling exposure time, development time and/or post exposure bake time based on data generated from examining the latent image.
Integrated circuits require ever more precise features. Manufacturing more precise features requires more precise control of the surface geometry, such as comers and edges, of features. When feature sizes become smaller, ensuring that exposure time, development time and/or post exposure bake time will produce a pattern with desired critical dimensions on a wafer becomes more important.
The process of manufacturing semiconductors involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The precision with which the electrically active regions can be created is important in achieving desired critical dimensions in the chips. Such precision is affected by the ability to control exposure, development and post exposure baking properties.
An exposure of a pattern may produce a latent image in a photo resist that, if exposed to inappropriate post exposure development conditions and/or post exposure baking conditions, may not produce desired critical dimensions, thus reducing chip manufacturing efficiency and chip quality. Exposure time can affect such the critical dimensions that will be achieved when a pattern is exposed, as can development properties (e.g., time, temperature) and post exposure bake properties (e.g., time, temperature). One or more patterns may be exposed on several layers formed (e.g., deposited and/or grown) on a wafer. Each such pattern may be affected by variations in a wafer (e.g., center to edge variations). Thus, a first exposure time that can be employed to expose a first pattern on a first layer and achieve acceptable critical dimensions, may not be similarly achieve acceptable critical dimensions for a second pattern on a second layer.
Similarly, a first set of development properties and/or a first set of post exposure bake properties that can be employed to develop and bake a first pattern on a first layer with acceptable critical dimensions may not similarly achieve acceptable critical dimensions for a second pattern on a second layer, due to wafer to wafer variations, variations between lots of wafers, and/or variations in prior manufacturing steps (e.g., exposure). Uniformity of critical dimensions between layers can improve IC quality leading to higher clocking speeds and resulting improved performance for such ICs.
Exposing the photo resist with the mask pattern produces a latent image on the photo resist. The intensity of the light, the length of exposure, and the focusing of the lens affect the properties of the latent image on the resist (e.g., depth of features, width of features, slope of feature edges). Conventionally, the exposure properties (e.g., length of exposure, dose, intensity) were pre-calculated. Such pre-determined calculations may not produce exposure conditions that will yield desired critical dimensions due to, for example, variations between wafers. Thus, patterns may be produced with features that whose critical dimensions do not fall within expected ranges. Departures from expected properties in the latent image produced on the photo resist may produce undesired results in subsequent manufacturing steps (e g., overexposure creating features that are too deep, underexposure creating features that are too shallow). Conventionally, development properties and/or post exposure properties may similarly be pre-calculated, not based on in situ information gathered from the latent image exposed on the photo resist.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention nor is it intended to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system that facilitates monitoring the exposure of a pattern into a photo resist, and the latent image produced by such exposure, in semiconductor manufacturing. The present invention further provides a system that facilitates generating information from analysis of the light reflected from the latent image in the resist layer and feeding forward such generated information to control a subsequent development process and/or a subsequent post exposure process. Monitoring and controlling the exposure with runtime feedback provides superior exposure control and thus facilitates achieving desired critical dimensions, with substantial uniformity in such critical dimensions between layers. Similarly, controlling subsequent manufacturing processes and/or apparatus based on data collected from monitoring a previous manufacturing process facilitates accounting for variations between wafers and/or variations between exposures, which facilitates achieving desired critical dimensions.
An exemplary system may employ an exposing system that includes one or more light sources arranged to project light onto a latent image exposed on a photo resist. The latent image may include one or more gratings on one or more portions of a wafer, the gratings facilitating analyzing properties of the latent image exposed in the photo resist. The system may also include one or more light sensing devices (e.g., photo detector, photodiode) for detecting light reflected by, and/or allowed to pass through, the latent image and/or one or more gratings in the latent image. The light reflected from, and/or passing through the latent image and/or one or more gratings in the latent image is indicative of at least one parameter of the exposure (e.g., depth dimensions, width dimensions, chemical composition changes). The determined parameters can then be employed to determine properties associated with developing the pattern exposed into the photo resist and feeding forward control information based on such determinations to the subsequent development process. Similarly, the determined parameters can be employed to determine properties associated with baking the pattern exposed into the photo resist and feeding forward control information based on such determinations to the subsequent baking process. Thus, subsequent manufacturing processes can respond to the actual manufacturing results produced in prior manufacturing processes, facilitating calculating more optimal conditions for the subsequent processes, resulting in higher quality, more uniform chips.
An exposing system is arranged to facilitate projecting a pattern onto a layer on a wafer. The exposing system may be, for example, a light and lens combination found in a stepper apparatus. It is to be appreciated that any suitable exposing system can be employed with the present invention. Exposure systems may to change exposure conditions including, but not limited to, duration, focus, phase, intensity and dose. Thus, exposure conditions may not be identical from exposure to exposure. Therefore, the results of exposing a pattern into a photo resist layer may vary from exposure to exposure. Further, there may be variations between wafers, again leading to variations between exposures. The latent image produced by an exposure can be analyzed by comparing signatures generated by the light reflected and/or passed through the latent image and/or gratings in the latent image to desired signatures. By comparing desired signatures to measured signatures, runtime feedback can be employed to more precisely control exposure. Similarly, by comparing desired signatures to measured signatures, runtime feed forward information can be generated that facilitates controlling subsequent manufacturing processes. Such feeding back and feeding forward facilitates achieving desired critical dimensions in the pattern to be developed on the wafer, which in turn increases fidelity of image transfer. The increased fidelity can lead to achieving desired critical dimensions, and can further lead to substantial uniformity of critical dimensions between layers, which in turn facilitates achieving higher speeds in such chips.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.